Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted to a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, imager devices, and interconnecting circuitry. The die also typically includes bond pads electrically coupled to the functional features. The bond pads are electrically connected to pins or other types of terminals that extend outside the protective covering for connecting the die to busses, circuits, and/or other microelectronic assemblies.
In one conventional arrangement, the die is mounted to a supporting substrate (e.g., a printed circuit board), and the die bond pads are electrically coupled to corresponding bond pads of the substrate with wirebonds. After encapsulation, the substrate can be electrically connected to external devices with solder balls or other suitable connections. Accordingly, the substrate both supports the die and provides an electrical link between the die and the external devices.
In other conventional arrangements, the die can be mounted to a leadframe that has conductive leadfingers connected to a removable frame. The frame temporarily supports the leadfingers in position relative to the die during manufacture. Each leadfinger is wirebonded to a corresponding bond pad of the die, and the assembly is encapsulated in such a way that the frame and a portion of each of the leadfingers extends outside the encapsulating material. The frame is then trimmed off, and the exposed portions of each leadfinger can be used to provide connections between the die and external devices.
FIG. 1A is a partially schematic, cross-sectional illustration of a package 50a configured in accordance with the prior art. The package 50a includes a die 10 that has an upwardly facing imager 11 and is supported from below by an insulating (e.g., ceramic) base 27. Leadfingers 23a are positioned around all four sides of the die 10 in a “quad flat no lead” (QFN) configuration, and are connected to the die 10 with wirebonds 40. Insulating standoffs 3 form a cavity 4 in which the die 10 is positioned, and support a glass window 30 over the imager 11. The window 30 provides a hermetically sealed package that transmits visible light to the imager 11. FIG. 1B illustrates another package 50b configured in accordance with the prior art. In this arrangement, the die 10 is carried by leads 23b. The glass window 30 is attached to the die 10 with an adhesive 31, and an encapsulant 41 is disposed over a portion of the die 10, the leads 23b, and the wirebonds 40 to protect these components.
Both arrangements for the packages 50a, 50b are suitable for installations in digital cameras, sensors, and/or other such devices. While the arrangements shown in FIG. 1A-1B have proven suitable for many applications, there remains a need to still further reduce the size of the package and the costs associated with manufacturing the package.